Circuits & Systems Classroom

Bang-bang PLL

A bang-bang PLL's phase detector answers one bit: late or early. Each answer moves the DCO by the same fixed step, however large the error was.

1 · Late or early? →e = 0.00 ps; only its sign is keptlate · +1
2 · Digital P + I →±400 kHz now, ±4 kHz kept; acts 1 cycle laterI = 0 kHz
3 · DCO →f − N·f_ref = offset + I ± β2000 kHz
4 · Divide by 40 ↴The edge moves −f·T_ref / f_out each cycle−5.00 ps
← divided DCO edge returns to the detector ←
late → +1early → −1 what the detector saw, with reference jitter cycle 0
159 pse = 0−159 psdecisionapplied, D = 1
Acquiring frequency: slewing 4.0 kHz per cycle Each correction moves the edge by Δ = β·T_ref / f_out = 1.00 ps per cycle. The strip shows the cycles around the cursor; the arrow follows this cycle's decision to the DCO.

Slew, not exponential. The DCO starts 2.0 MHz fast. Every decision says early, and a one-bit detector cannot say how early, so the integral path walks the frequency down by α = 4 kHz per cycle: a straight ramp. The frequency error is gone after 402 cycles, but by then the edge is 814 ps early. The decisions still say early, so the ramp runs on past zero until that phase is paid back, and turns again. The error settles after about 1202 cycles (12.0 µs).

400 kHz
4 kHz
Latency D (reference cycles)
2.0 MHz
0.30 ps
-95 dBc/Hz
Noise

f_ref = 100 MHz, N = 40, f_out = 4 GHz. DCO noise random-walks the edge by 0.44 ps rms per cycle. Pull-in ≈ 4.40 MHz.

cycle 0 · 0.00 µs

Frequency: a ramp, then hopping ±β

DCOoffset + integral path
-30000-150010020150030300040f − N·f_ref · kHztime · µs

Phase error at every reference edge

e (late > 0)
-10000-5001002050030100040e · pstime · µs

Second half: 1.24 ps rms, 7.07 ps peak to peak.

The detector: a sign, smoothed by jitter

sign aloneerf(e / σ√2), σ = 0.3 psslope √(2/π)/σthis run, averaged per bin
-1-2-0.5-1000.5112average decisione · ps

With jitter the average answer grows smoothly with e: 2.66 per ps near zero.

Jitter against the step size

rms jitter with noiselimit cycle alone, no noiseβ now
01.252.53.75525501002004008001600rms e · psβ · kHz (log)

Lowest of these at β = 100 kHz (0.87 ps rms). Smaller steps fall behind the DCO's random walk; larger ones make a larger limit cycle. Each point averages three noise seeds over 10 000 settled cycles, starting locked, with α/β kept at the current ratio.

Model and related lessons

A cycle-by-cycle model at the reference rate. The timing error e is the divided DCO edge minus the reference edge. A DCO frequency error f moves the next edge by −f·T_ref / f_out, 0.0025 ps per kHz per cycle. The detector compares each reference edge with the nearest feedback edge, so e wraps at ±T_ref / 2 = ±5 ns: a cycle slip. Reference jitter is white and enters only at the detector; the DCO's white FM noise L(1 MHz) adds a random walk of (1 MHz / f_out)·√(10^(L/10) / f_ref) per cycle. The integral path acts with the same latency as the proportional path. Not modelled: DCO quantization and its ΣΔ dithering, detector metastability, frequency-acquisition aids and divider retiming. python/pll_bang_bang.py reproduces each run exactly and checks the limit-cycle, pull-in and erf formulas against the simulation.

Start with a linear detector in the PLL introduction. The same one-bit detector recovers a receiver's clock in Clock and data recovery. Next: Integer-N vs fractional-N.